In the manufacture of semiconductor integrated circuit devices a variety of techniques are known for constructing different electrical interconnect features. For example, features, such as line traces, trenches, and via formations, form the conductive paths horizontally and vertically on a semiconductor substrate. As the density of devices increase significantly, new techniques are developed to increase interconnect density without substantial impact to cost, throughput and complexity in manufacturing. Accordingly new techniques which increase wiring or feature density, with the added benefit of reducing manufacturing complexity and/or costs, are an attractive advantage.
In the formation of various interconnect features, a typical practice is to use a photolithographic process for patterning and developing a photoresistive material (photoresist) to define the various interconnect features. For example, in one technique, a uniform layer of a conductor, such as copper, is formed on a dielectric layer and then coated with photoresist. Subsequently, masking and lithography are employed to pattern the photoresist. Then, the photoresist is developed so that the pattern is transferred to the copper material to identify underlying features and the remaining copper forms the conductive regions, such as line traces, on the surface of the dielectric. Openings are formed in the dielectric at various locations for the formation of vias. Vias extending completely through the dielectric layer allow for an electrical path from regions above the dielectric layer to those regions under the dielectric layer. The usage of various interconnecting features, as well as the use of pattern lithography to form such features, are generally known in the art.
In another example using the photoresist/lithography technique to form interconnects, a copper sheet is used to clad a dielectric core on both the upper and lower surfaces. Subsequently, the photoresist layer is deposited and masking and photolithography are used to pattern the photoresist. Next, the photoresist is developed to define the features and these features are exposed with the stripping of the photoresist. Subsequently, the assembly is laminated to cover the formed traces. Next, a laser micro via and mechanical drilling techniques are used to drill openings through the lamination to expose the trace or, alternatively, the drilling is performed completely through the lamination and to the core so that an opening extends completely through from the top surface. The procedure is then followed by a plating technique in which the exposed regions are plated. Generally, this technique will cover the exposed traces along the surface of the core but the vias extending through from the top to the bottom surface still remain, although the surfaces are plated. Next the vias are then plugged with a conductive material and the excess material is removed, by procedures such as grinding. Finally, a lid plating process is used to cover the upper and bottom surfaces of the plated hole. Further patterning may then be used to identify the conductive regions. Similar photoresist, masking, lithography procedures, as earlier described above, may be employed to pattern and define the traces along the upper and/or lower surfaces of the assembly.